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asm_ppc64le.s

asm_ppc64le.s 9.3 KB
永久連結 文件歷史 原始文件

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  1. // Copyright 2019 The Go Authors. All rights reserved.
    2. 

  2. // Use of this source code is governed by a BSD-style
    3. 

  3. // license that can be found in the LICENSE file.
    4. 

  4. 

  5. // Based on CRYPTOGAMS code with the following comment:
    6. 

  6. // # ====================================================================
    7. 

  7. // # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
    8. 

  8. // # project. The module is, however, dual licensed under OpenSSL and
    9. 

  9. // # CRYPTOGAMS licenses depending on where you obtain it. For further
    10. 

  10. // # details see http://www.openssl.org/~appro/cryptogams/.
    11. 

  11. // # ====================================================================
    12. 

  12. 

  13. // Code for the perl script that generates the ppc64 assembler
    14. 

  14. // can be found in the cryptogams repository at the link below. It is based on
    15. 

  15. // the original from openssl.
    16. 

  16. 

  17. // https://github.com/dot-asm/cryptogams/commit/a60f5b50ed908e91
    18. 

  18. 

  19. // The differences in this and the original implementation are
    20. 

  20. // due to the calling conventions and initialization of constants.
    21. 

  21. 

  22. // +build ppc64le,!gccgo,!appengine
    23. 

  23. 

  24. #include "textflag.h"
    25. 

  25. 

  26. #define OUT  R3
    27. 

  27. #define INP  R4
    28. 

  28. #define LEN  R5
    29. 

  29. #define KEY  R6
    30. 

  30. #define CNT  R7
    31. 

  31. #define TMP  R15
    32. 

  32. 

  33. #define CONSTBASE  R16
    34. 

  34. 

  35. #define X0   R11
    36. 

  36. #define X1   R12
    37. 

  37. #define X2   R14
    38. 

  38. #define X3   R15
    39. 

  39. #define X4   R16
    40. 

  40. #define X5   R17
    41. 

  41. #define X6   R18
    42. 

  42. #define X7   R19
    43. 

  43. #define X8   R20
    44. 

  44. #define X9   R21
    45. 

  45. #define X10  R22
    46. 

  46. #define X11  R23
    47. 

  47. #define X12  R24
    48. 

  48. #define X13  R25
    49. 

  49. #define X14  R26
    50. 

  50. #define X15  R27
    51. 

  51. 

  52. 

  53. DATA consts<>+0x00(SB)/8, $0x3320646e61707865
    54. 

  54. DATA consts<>+0x08(SB)/8, $0x6b20657479622d32
    55. 

  55. DATA consts<>+0x10(SB)/8, $0x0000000000000001
    56. 

  56. DATA consts<>+0x18(SB)/8, $0x0000000000000000
    57. 

  57. DATA consts<>+0x20(SB)/8, $0x0000000000000004
    58. 

  58. DATA consts<>+0x28(SB)/8, $0x0000000000000000
    59. 

  59. DATA consts<>+0x30(SB)/8, $0x0a0b08090e0f0c0d
    60. 

  60. DATA consts<>+0x38(SB)/8, $0x0203000106070405
    61. 

  61. DATA consts<>+0x40(SB)/8, $0x090a0b080d0e0f0c
    62. 

  62. DATA consts<>+0x48(SB)/8, $0x0102030005060704
    63. 

  63. DATA consts<>+0x50(SB)/8, $0x6170786561707865
    64. 

  64. DATA consts<>+0x58(SB)/8, $0x6170786561707865
    65. 

  65. DATA consts<>+0x60(SB)/8, $0x3320646e3320646e
    66. 

  66. DATA consts<>+0x68(SB)/8, $0x3320646e3320646e
    67. 

  67. DATA consts<>+0x70(SB)/8, $0x79622d3279622d32
    68. 

  68. DATA consts<>+0x78(SB)/8, $0x79622d3279622d32
    69. 

  69. DATA consts<>+0x80(SB)/8, $0x6b2065746b206574
    70. 

  70. DATA consts<>+0x88(SB)/8, $0x6b2065746b206574
    71. 

  71. DATA consts<>+0x90(SB)/8, $0x0000000100000000
    72. 

  72. DATA consts<>+0x98(SB)/8, $0x0000000300000002
    73. 

  73. GLOBL consts<>(SB), RODATA, $0xa0
    74. 

  74. 

  75. //func chaCha20_ctr32_vsx(out, inp []byte, len int, key *[32]byte, counter *[16]byte)
    76. 

  76. TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
    77. 

  77. 	MOVD out+0(FP), OUT
    78. 

  78. 	MOVD inp+8(FP), INP
    79. 

  79. 	MOVD len+16(FP), LEN
    80. 

  80. 	MOVD key+24(FP), KEY
    81. 

  81. 	MOVD cnt+32(FP), CNT
    82. 

  82. 

  83. 	// Addressing for constants
    84. 

  84. 	MOVD $consts<>+0x00(SB), CONSTBASE
    85. 

  85. 	MOVD $16, R8
    86. 

  86. 	MOVD $32, R9
    87. 

  87. 	MOVD $48, R10
    88. 

  88. 	MOVD $64, R11
    89. 

  89. 	// V16
    90. 

  90. 	LXVW4X (CONSTBASE)(R0), VS48
    91. 

  91. 	ADD $80,CONSTBASE
    92. 

  92. 

  93. 	// Load key into V17,V18
    94. 

  94. 	LXVW4X (KEY)(R0), VS49
    95. 

  95. 	LXVW4X (KEY)(R8), VS50
    96. 

  96. 

  97. 	// Load CNT, NONCE into V19
    98. 

  98. 	LXVW4X (CNT)(R0), VS51
    99. 

  99. 

  100. 	// Clear V27
    101. 

  101. 	VXOR V27, V27, V27
    102. 

  102. 

  103. 	// V28
    104. 

  104. 	LXVW4X (CONSTBASE)(R11), VS60
    105. 

  105. 

  106. 	// splat slot from V19 -> V26
    107. 

  107. 	VSPLTW $0, V19, V26
    108. 

  108. 

  109. 	VSLDOI $4, V19, V27, V19
    110. 

  110. 	VSLDOI $12, V27, V19, V19
    111. 

  111. 

  112. 	VADDUWM V26, V28, V26
    113. 

  113. 

  114. 	MOVD $10, R14
    115. 

  115. 	MOVD R14, CTR
    116. 

  116. 

  117. loop_outer_vsx:
    118. 

  118. 	// V0, V1, V2, V3
    119. 

  119. 	LXVW4X (R0)(CONSTBASE), VS32
    120. 

  120. 	LXVW4X (R8)(CONSTBASE), VS33
    121. 

  121. 	LXVW4X (R9)(CONSTBASE), VS34
    122. 

  122. 	LXVW4X (R10)(CONSTBASE), VS35
    123. 

  123. 

  124. 	// splat values from V17, V18 into V4-V11
    125. 

  125. 	VSPLTW $0, V17, V4
    126. 

  126. 	VSPLTW $1, V17, V5
    127. 

  127. 	VSPLTW $2, V17, V6
    128. 

  128. 	VSPLTW $3, V17, V7
    129. 

  129. 	VSPLTW $0, V18, V8
    130. 

  130. 	VSPLTW $1, V18, V9
    131. 

  131. 	VSPLTW $2, V18, V10
    132. 

  132. 	VSPLTW $3, V18, V11
    133. 

  133. 

  134. 	// VOR
    135. 

  135. 	VOR V26, V26, V12
    136. 

  136. 

  137. 	// splat values from V19 -> V13, V14, V15
    138. 

  138. 	VSPLTW $1, V19, V13
    139. 

  139. 	VSPLTW $2, V19, V14
    140. 

  140. 	VSPLTW $3, V19, V15
    141. 

  141. 

  142. 	// splat   const values
    143. 

  143. 	VSPLTISW $-16, V27
    144. 

  144. 	VSPLTISW $12, V28
    145. 

  145. 	VSPLTISW $8, V29
    146. 

  146. 	VSPLTISW $7, V30
    147. 

  147. 

  148. loop_vsx:
    149. 

  149. 	VADDUWM V0, V4, V0
    150. 

  150. 	VADDUWM V1, V5, V1
    151. 

  151. 	VADDUWM V2, V6, V2
    152. 

  152. 	VADDUWM V3, V7, V3
    153. 

  153. 

  154. 	VXOR V12, V0, V12
    155. 

  155. 	VXOR V13, V1, V13
    156. 

  156. 	VXOR V14, V2, V14
    157. 

  157. 	VXOR V15, V3, V15
    158. 

  158. 

  159. 	VRLW V12, V27, V12
    160. 

  160. 	VRLW V13, V27, V13
    161. 

  161. 	VRLW V14, V27, V14
    162. 

  162. 	VRLW V15, V27, V15
    163. 

  163. 

  164. 	VADDUWM V8, V12, V8
    165. 

  165. 	VADDUWM V9, V13, V9
    166. 

  166. 	VADDUWM V10, V14, V10
    167. 

  167. 	VADDUWM V11, V15, V11
    168. 

  168. 

  169. 	VXOR V4, V8, V4
    170. 

  170. 	VXOR V5, V9, V5
    171. 

  171. 	VXOR V6, V10, V6
    172. 

  172. 	VXOR V7, V11, V7
    173. 

  173. 

  174. 	VRLW V4, V28, V4
    175. 

  175. 	VRLW V5, V28, V5
    176. 

  176. 	VRLW V6, V28, V6
    177. 

  177. 	VRLW V7, V28, V7
    178. 

  178. 

  179. 	VADDUWM V0, V4, V0
    180. 

  180. 	VADDUWM V1, V5, V1
    181. 

  181. 	VADDUWM V2, V6, V2
    182. 

  182. 	VADDUWM V3, V7, V3
    183. 

  183. 

  184. 	VXOR V12, V0, V12
    185. 

  185. 	VXOR V13, V1, V13
    186. 

  186. 	VXOR V14, V2, V14
    187. 

  187. 	VXOR V15, V3, V15
    188. 

  188. 

  189. 	VRLW V12, V29, V12
    190. 

  190. 	VRLW V13, V29, V13
    191. 

  191. 	VRLW V14, V29, V14
    192. 

  192. 	VRLW V15, V29, V15
    193. 

  193. 

  194. 	VADDUWM V8, V12, V8
    195. 

  195. 	VADDUWM V9, V13, V9
    196. 

  196. 	VADDUWM V10, V14, V10
    197. 

  197. 	VADDUWM V11, V15, V11
    198. 

  198. 

  199. 	VXOR V4, V8, V4
    200. 

  200. 	VXOR V5, V9, V5
    201. 

  201. 	VXOR V6, V10, V6
    202. 

  202. 	VXOR V7, V11, V7
    203. 

  203. 

  204. 	VRLW V4, V30, V4
    205. 

  205. 	VRLW V5, V30, V5
    206. 

  206. 	VRLW V6, V30, V6
    207. 

  207. 	VRLW V7, V30, V7
    208. 

  208. 

  209. 	VADDUWM V0, V5, V0
    210. 

  210. 	VADDUWM V1, V6, V1
    211. 

  211. 	VADDUWM V2, V7, V2
    212. 

  212. 	VADDUWM V3, V4, V3
    213. 

  213. 

  214. 	VXOR V15, V0, V15
    215. 

  215. 	VXOR V12, V1, V12
    216. 

  216. 	VXOR V13, V2, V13
    217. 

  217. 	VXOR V14, V3, V14
    218. 

  218. 

  219. 	VRLW V15, V27, V15
    220. 

  220. 	VRLW V12, V27, V12
    221. 

  221. 	VRLW V13, V27, V13
    222. 

  222. 	VRLW V14, V27, V14
    223. 

  223. 

  224. 	VADDUWM V10, V15, V10
    225. 

  225. 	VADDUWM V11, V12, V11
    226. 

  226. 	VADDUWM V8, V13, V8
    227. 

  227. 	VADDUWM V9, V14, V9
    228. 

  228. 

  229. 	VXOR V5, V10, V5
    230. 

  230. 	VXOR V6, V11, V6
    231. 

  231. 	VXOR V7, V8, V7
    232. 

  232. 	VXOR V4, V9, V4
    233. 

  233. 

  234. 	VRLW V5, V28, V5
    235. 

  235. 	VRLW V6, V28, V6
    236. 

  236. 	VRLW V7, V28, V7
    237. 

  237. 	VRLW V4, V28, V4
    238. 

  238. 

  239. 	VADDUWM V0, V5, V0
    240. 

  240. 	VADDUWM V1, V6, V1
    241. 

  241. 	VADDUWM V2, V7, V2
    242. 

  242. 	VADDUWM V3, V4, V3
    243. 

  243. 

  244. 	VXOR V15, V0, V15
    245. 

  245. 	VXOR V12, V1, V12
    246. 

  246. 	VXOR V13, V2, V13
    247. 

  247. 	VXOR V14, V3, V14
    248. 

  248. 

  249. 	VRLW V15, V29, V15
    250. 

  250. 	VRLW V12, V29, V12
    251. 

  251. 	VRLW V13, V29, V13
    252. 

  252. 	VRLW V14, V29, V14
    253. 

  253. 

  254. 	VADDUWM V10, V15, V10
    255. 

  255. 	VADDUWM V11, V12, V11
    256. 

  256. 	VADDUWM V8, V13, V8
    257. 

  257. 	VADDUWM V9, V14, V9
    258. 

  258. 

  259. 	VXOR V5, V10, V5
    260. 

  260. 	VXOR V6, V11, V6
    261. 

  261. 	VXOR V7, V8, V7
    262. 

  262. 	VXOR V4, V9, V4
    263. 

  263. 

  264. 	VRLW V5, V30, V5
    265. 

  265. 	VRLW V6, V30, V6
    266. 

  266. 	VRLW V7, V30, V7
    267. 

  267. 	VRLW V4, V30, V4
    268. 

  268. 	BC   16, LT, loop_vsx
    269. 

  269. 

  270. 	VADDUWM V12, V26, V12
    271. 

  271. 

  272. 	WORD $0x13600F8C		// VMRGEW V0, V1, V27
    273. 

  273. 	WORD $0x13821F8C		// VMRGEW V2, V3, V28
    274. 

  274. 

  275. 	WORD $0x10000E8C		// VMRGOW V0, V1, V0
    276. 

  276. 	WORD $0x10421E8C		// VMRGOW V2, V3, V2
    277. 

  277. 

  278. 	WORD $0x13A42F8C		// VMRGEW V4, V5, V29
    279. 

  279. 	WORD $0x13C63F8C		// VMRGEW V6, V7, V30
    280. 

  280. 

  281. 	XXPERMDI VS32, VS34, $0, VS33
    282. 

  282. 	XXPERMDI VS32, VS34, $3, VS35
    283. 

  283. 	XXPERMDI VS59, VS60, $0, VS32
    284. 

  284. 	XXPERMDI VS59, VS60, $3, VS34
    285. 

  285. 

  286. 	WORD $0x10842E8C		// VMRGOW V4, V5, V4
    287. 

  287. 	WORD $0x10C63E8C		// VMRGOW V6, V7, V6
    288. 

  288. 

  289. 	WORD $0x13684F8C		// VMRGEW V8, V9, V27
    290. 

  290. 	WORD $0x138A5F8C		// VMRGEW V10, V11, V28
    291. 

  291. 

  292. 	XXPERMDI VS36, VS38, $0, VS37
    293. 

  293. 	XXPERMDI VS36, VS38, $3, VS39
    294. 

  294. 	XXPERMDI VS61, VS62, $0, VS36
    295. 

  295. 	XXPERMDI VS61, VS62, $3, VS38
    296. 

  296. 

  297. 	WORD $0x11084E8C		// VMRGOW V8, V9, V8
    298. 

  298. 	WORD $0x114A5E8C		// VMRGOW V10, V11, V10
    299. 

  299. 

  300. 	WORD $0x13AC6F8C		// VMRGEW V12, V13, V29
    301. 

  301. 	WORD $0x13CE7F8C		// VMRGEW V14, V15, V30
    302. 

  302. 

  303. 	XXPERMDI VS40, VS42, $0, VS41
    304. 

  304. 	XXPERMDI VS40, VS42, $3, VS43
    305. 

  305. 	XXPERMDI VS59, VS60, $0, VS40
    306. 

  306. 	XXPERMDI VS59, VS60, $3, VS42
    307. 

  307. 

  308. 	WORD $0x118C6E8C		// VMRGOW V12, V13, V12
    309. 

  309. 	WORD $0x11CE7E8C		// VMRGOW V14, V15, V14
    310. 

  310. 

  311. 	VSPLTISW $4, V27
    312. 

  312. 	VADDUWM V26, V27, V26
    313. 

  313. 

  314. 	XXPERMDI VS44, VS46, $0, VS45
    315. 

  315. 	XXPERMDI VS44, VS46, $3, VS47
    316. 

  316. 	XXPERMDI VS61, VS62, $0, VS44
    317. 

  317. 	XXPERMDI VS61, VS62, $3, VS46
    318. 

  318. 

  319. 	VADDUWM V0, V16, V0
    320. 

  320. 	VADDUWM V4, V17, V4
    321. 

  321. 	VADDUWM V8, V18, V8
    322. 

  322. 	VADDUWM V12, V19, V12
    323. 

  323. 

  324. 	CMPU LEN, $64
    325. 

  325. 	BLT tail_vsx
    326. 

  326. 

  327. 	// Bottom of loop
    328. 

  328. 	LXVW4X (INP)(R0), VS59
    329. 

  329. 	LXVW4X (INP)(R8), VS60
    330. 

  330. 	LXVW4X (INP)(R9), VS61
    331. 

  331. 	LXVW4X (INP)(R10), VS62
    332. 

  332. 

  333. 	VXOR V27, V0, V27
    334. 

  334. 	VXOR V28, V4, V28
    335. 

  335. 	VXOR V29, V8, V29
    336. 

  336. 	VXOR V30, V12, V30
    337. 

  337. 

  338. 	STXVW4X VS59, (OUT)(R0)
    339. 

  339. 	STXVW4X VS60, (OUT)(R8)
    340. 

  340. 	ADD     $64, INP
    341. 

  341. 	STXVW4X VS61, (OUT)(R9)
    342. 

  342. 	ADD     $-64, LEN
    343. 

  343. 	STXVW4X VS62, (OUT)(R10)
    344. 

  344. 	ADD     $64, OUT
    345. 

  345. 	BEQ     done_vsx
    346. 

  346. 

  347. 	VADDUWM V1, V16, V0
    348. 

  348. 	VADDUWM V5, V17, V4
    349. 

  349. 	VADDUWM V9, V18, V8
    350. 

  350. 	VADDUWM V13, V19, V12
    351. 

  351. 

  352. 	CMPU  LEN, $64
    353. 

  353. 	BLT   tail_vsx
    354. 

  354. 

  355. 	LXVW4X (INP)(R0), VS59
    356. 

  356. 	LXVW4X (INP)(R8), VS60
    357. 

  357. 	LXVW4X (INP)(R9), VS61
    358. 

  358. 	LXVW4X (INP)(R10), VS62
    359. 

  359. 	VXOR   V27, V0, V27
    360. 

  360. 

  361. 	VXOR V28, V4, V28
    362. 

  362. 	VXOR V29, V8, V29
    363. 

  363. 	VXOR V30, V12, V30
    364. 

  364. 

  365. 	STXVW4X VS59, (OUT)(R0)
    366. 

  366. 	STXVW4X VS60, (OUT)(R8)
    367. 

  367. 	ADD     $64, INP
    368. 

  368. 	STXVW4X VS61, (OUT)(R9)
    369. 

  369. 	ADD     $-64, LEN
    370. 

  370. 	STXVW4X VS62, (OUT)(V10)
    371. 

  371. 	ADD     $64, OUT
    372. 

  372. 	BEQ     done_vsx
    373. 

  373. 

  374. 	VADDUWM V2, V16, V0
    375. 

  375. 	VADDUWM V6, V17, V4
    376. 

  376. 	VADDUWM V10, V18, V8
    377. 

  377. 	VADDUWM V14, V19, V12
    378. 

  378. 

  379. 	CMPU LEN, $64
    380. 

  380. 	BLT  tail_vsx
    381. 

  381. 

  382. 	LXVW4X (INP)(R0), VS59
    383. 

  383. 	LXVW4X (INP)(R8), VS60
    384. 

  384. 	LXVW4X (INP)(R9), VS61
    385. 

  385. 	LXVW4X (INP)(R10), VS62
    386. 

  386. 

  387. 	VXOR V27, V0, V27
    388. 

  388. 	VXOR V28, V4, V28
    389. 

  389. 	VXOR V29, V8, V29
    390. 

  390. 	VXOR V30, V12, V30
    391. 

  391. 

  392. 	STXVW4X VS59, (OUT)(R0)
    393. 

  393. 	STXVW4X VS60, (OUT)(R8)
    394. 

  394. 	ADD     $64, INP
    395. 

  395. 	STXVW4X VS61, (OUT)(R9)
    396. 

  396. 	ADD     $-64, LEN
    397. 

  397. 	STXVW4X VS62, (OUT)(R10)
    398. 

  398. 	ADD     $64, OUT
    399. 

  399. 	BEQ     done_vsx
    400. 

  400. 

  401. 	VADDUWM V3, V16, V0
    402. 

  402. 	VADDUWM V7, V17, V4
    403. 

  403. 	VADDUWM V11, V18, V8
    404. 

  404. 	VADDUWM V15, V19, V12
    405. 

  405. 

  406. 	CMPU  LEN, $64
    407. 

  407. 	BLT   tail_vsx
    408. 

  408. 

  409. 	LXVW4X (INP)(R0), VS59
    410. 

  410. 	LXVW4X (INP)(R8), VS60
    411. 

  411. 	LXVW4X (INP)(R9), VS61
    412. 

  412. 	LXVW4X (INP)(R10), VS62
    413. 

  413. 

  414. 	VXOR V27, V0, V27
    415. 

  415. 	VXOR V28, V4, V28
    416. 

  416. 	VXOR V29, V8, V29
    417. 

  417. 	VXOR V30, V12, V30
    418. 

  418. 

  419. 	STXVW4X VS59, (OUT)(R0)
    420. 

  420. 	STXVW4X VS60, (OUT)(R8)
    421. 

  421. 	ADD     $64, INP
    422. 

  422. 	STXVW4X VS61, (OUT)(R9)
    423. 

  423. 	ADD     $-64, LEN
    424. 

  424. 	STXVW4X VS62, (OUT)(R10)
    425. 

  425. 	ADD     $64, OUT
    426. 

  426. 

  427. 	MOVD $10, R14
    428. 

  428. 	MOVD R14, CTR
    429. 

  429. 	BNE  loop_outer_vsx
    430. 

  430. 

  431. done_vsx:
    432. 

  432. 	// Increment counter by 4
    433. 

  433. 	MOVD (CNT), R14
    434. 

  434. 	ADD  $4, R14
    435. 

  435. 	MOVD R14, (CNT)
    436. 

  436. 	RET
    437. 

  437. 

  438. tail_vsx:
    439. 

  439. 	ADD  $32, R1, R11
    440. 

  440. 	MOVD LEN, CTR
    441. 

  441. 

  442. 	// Save values on stack to copy from
    443. 

  443. 	STXVW4X VS32, (R11)(R0)
    444. 

  444. 	STXVW4X VS36, (R11)(R8)
    445. 

  445. 	STXVW4X VS40, (R11)(R9)
    446. 

  446. 	STXVW4X VS44, (R11)(R10)
    447. 

  447. 	ADD $-1, R11, R12
    448. 

  448. 	ADD $-1, INP
    449. 

  449. 	ADD $-1, OUT
    450. 

  450. 

  451. looptail_vsx:
    452. 

  452. 	// Copying the result to OUT
    453. 

  453. 	// in bytes.
    454. 

  454. 	MOVBZU 1(R12), KEY
    455. 

  455. 	MOVBZU 1(INP), TMP
    456. 

  456. 	XOR    KEY, TMP, KEY
    457. 

  457. 	MOVBU  KEY, 1(OUT)
    458. 

  458. 	BC     16, LT, looptail_vsx
    459. 

  459. 

  460. 	// Clear the stack values
    461. 

  461. 	STXVW4X VS48, (R11)(R0)
    462. 

  462. 	STXVW4X VS48, (R11)(R8)
    463. 

  463. 	STXVW4X VS48, (R11)(R9)
    464. 

  464. 	STXVW4X VS48, (R11)(R10)
    465. 

  465. 	BR      done_vsx
    466.